This invention relates generally to semiconductor fabrication processes, and more particularly to metalization of vias and trenches.
In modern semiconductor fabrication processes, multiple interconnect layers of metal, many times in the form of trenches, are often used to carry signals within a semiconductor device. Each layer is generally separated from the layers immediately above and below by a dielectric layer. However, signals often need to be transmitted between different layers as well as within individual metal layers.
Signal propagation between metal layers is often accomplished using vias. Vias consist of a metal trace, or plug, extending in a substantially vertical direction through a dielectric layer. On each side of the dielectric layer, the metal trace of the via contacts the metal layers separated by the dielectric. In this way, the via serves to electrically couple metal layers that are separated by a dielectric.
To form a via, an aperture is first formed in a dielectric layer, reaching a metal layer below. The via aperture is metalized, or filled with metal, in order to make good ohmic contact with the underlying metal layer. A second metal layer, contacting the via, is deposited above the via. Current is thus free to flow along one metal layer, through the via, and into the second metal layer. In most processes, vias are not restricted to coupling adjacent metal layers. It is possible for vias to couple two metal layers that are separated by one or more intermediate metal layers.
Vias are difficult to fabricate, and are particularly difficult to metalize properly. Properly metalized vias are preferably free from gaps, areas devoid of metalizaion, and areas of partial metalization. An area of a via lacking metalization such that the metal layers on each side of the via are not electrically coupled creates an electrical open circuit. Such an open circuit can lead to the failure of circuitry associated with the via. Partial metalization can increase the resistance associated with a via. Increased resistance in the via can cause associated circuitry to function at a reduced speed, as well as create reliability and other problems. In each of these cases, the semiconductor device may not meet the necessary specifications.
An example of a via containing a void can be seen in FIG. 1. Illustrated in FIG. 1 are two metal layers 2, 4, separated by a dielectric layer 6. A metal filled via 8 couples the two metal layers through the dielectric. The via, however, includes a void 10, with the void being a volume substantially devoid of metal. Thus, current traveling through the via must pass through the region between the periphery of the void 12 and the edge of the via 14. Via resistance may be increased due to the smaller cross-sectional area that the current must pass through. This can adversely affect the performance of the semiconductor device as discussed above. Additionally, due the reduced cross sectional area, the current density in the region adjacent to the void is increased.
Of particular importance in semiconductor fabrication is the yield of a product. Proper fabrication of vias and trenches is an important aspect of maintaining high yields. Product yield is simply the ratio of the number of semiconductor devices that meet specifications to the total number of that particular device that are produced. It is desirable to have as high a yield as possible. Unfilled or partially filled vias and trenches either prevent the semiconductor device from operating properly, or possibly require that the semiconductor device be operated at reduced speeds.
Furthermore, the reliability of semiconductor devices is of great importance. Many devices are expected to provide years of nearly continuous, trouble-free service. A void in a via increases the current density in an area of a via, as discussed above. Increased current density accelerates electromigration, the process by which the flow of current through a conductor gradually severs the conductor. A void and the resulting enhanced electromigration can thus lead to the premature failure of a via. A via failing in such a way often acts as an electrical open circuit, causing problems as previously discussed.
As processes and semiconductor speeds continue to become more aggressive, spacing between metal layers is increasing. That is, thicker dielectrics are often being used. Increased spacing between metal layers decreases parasitic capacitance on signal lines. Lower capacitance frequently allows circuits to be operated at higher speeds. However, as metal spacing increases, the required via height increases as well. Thus the via aspect ratio, the ratio of via height to width, increases. Narrower metal lines on semiconductor devices make smaller via diameters preferable. Each of these trends lead to increased via aspect ratios. As aspect ratios increase, vias generally become more difficult to metalize properly.
In order to completely metalize a via, the metal used, often aluminum, should reach the bottom of the via. As aspect ratios grow it becomes increasingly difficult to ensure that metal reaches and substantially fills the lowest levels of the via. In order to encourage the movement of metal into the bottom of the vias, high temperatures are often employed in the fabrication process. Higher temperatures decrease the viscosity of aluminum and facilitate its movement into and within the vias. These high temperatures cause high stresses to form in the substrate material and previously fabricated layers due to thermal expansion.
Modern semiconductor devices employ a variety of materials in their manufacture. These materials can have widely varying coefficients of thermal expansion. Such materials include aluminum or other metals, silicon dioxide and other dielectrics, silicon or other semiconductors, as well as polycrystalline and other connecting materials. Variations in the coefficients of thermal expansion can lead to different expansions and movements for different sections and materials of the semiconductor device. These differences in expansion and associated movement can cause the severing or degrading of connections within the semiconductor device. Ultimately, this may precipitate the failure of the final product.
The present invention provides a low temperature aluminum planarization process. The process is suitable for forming high aspect ratio vias and trenches. In one embodiment the process comprises a treatment of a semiconductor device so as to allow substantially completely filled vias and trenches. The treatment comprises cleaning an aperture of a semiconductor device, depositing a metal liner layer on the semiconductor device, and depositing a seed layer of aluminum of the metal liner layer. The process further comprises exposing the semiconductor device to a reactive gas, and depositing aluminum on the seed layer to fill the aperture. In one embodiment the via couples a plurality of metal layers through one or more dielectric layers. In a further embodiment the treatment comprises cleaning the via opening by exposing the via aperture and surrounding areas to a cleaning process. In one embodiment the metal liner layer comprises titanium based compounds, and in a further embodiment the metal liner layer includes titanium nitride. In a further embodiment depositing a seed layer of aluminum on the metal liner layer comprises depositing a layer of aluminum on the metal liner layer at a temperature such that the seed layer of aluminum does not amalgamate. In one embodiment the semiconductor device temperature onto which the seed layer of aluminum is deposited is below about 200 degrees centigrade. In a further embodiment exposing the semiconductor device to an atmosphere containing reactive gas comprises exposing the device to an atmosphere containing a mixture of reactive gases and inert gases.
These and other aspects of the present invention may be more readily understood through study of the following detailed description in conjunction with viewing of the accompanying figures.